Semiconductor device with ferro-electric capacitor

ABSTRACT

A semiconductor device has a ferro-electric capacitor with small leak current and less process deterioration even upon miniaturization. The semiconductor device includes: a semiconductor element formed in a semiconductor substrate; lamination of an interlayer insulating film and a lower insulating shielding film having a hydrogen/moisture shielding function, the lamination being formed covering the semiconductor element; a conductive adhesion enhancing film formed above the lower insulating shielding film; and a ferro-electric capacitor including a lower electrode formed above the conductive adhesion enhancing film, a ferro-electric film formed on the lower electrode and being disposed within the lower electrode as viewed in plan, and an upper electrode formed on the ferro-electric film and being disposed within the ferro-electric film as viewed in plan, wherein the conductive adhesion enhancing film has a function of improving adhesion of the lower electrode and reducing leak current of the ferro-electric capacitor.

This application is a divisional of U.S. patent application Ser. No.12/128,088, filed on May 28, 2008, which is a continuation applicationof International Patent Application PCT/JP2005/21854, filed on Nov. 29,2005, designating US as one of the designation countries, the entirecontents of which are incorporated herein by reference.

TECHNICAL FIELD

The embodiments discussed herein are directed to a semiconductor deviceand a manufacture method therof. The embodiments may relate to asemiconductor device having a ferro-electric capacitor and a manufacturemethod thereof.

BACKGROUND ART

With the recent advancement of digital technologies, there is a strongtendency toward high speed processing or storage of high capacity data,and a demand for high integration and high performance of semiconductordevices used in electronic apparatus. In order to realize highintegration of a semiconductor device, as a capacitor dielectric film ofa capacitor which forms a storage element, a high dielectric constantmaterial film or a ferro-electric material film is being used in placeof a conventional silicon oxide film or a silicon nitride film.

As a nonvolatile memory capable of high speed read/write at a lowvoltage, a ferro-electric random access memory (FeRAM) in particular hasbeen studied and developed vigorously which uses a ferro-electric filmhaving spontaneous polarization characteristics as a capacitordielectric film.

A ferro-electric memory (FeRAM) is a nonvolatile memory in which storedinformation will not be erased even if a power supply is shut down, andis expected to realize high integration, high speed driving, highdurability and low power consumption.

FeRAM stores information by utilizing hysteresis characteristics offerro-electric material. A ferro-electric capacitor having aferro-electric film as a capacitor dielectric film sandwiched between apair of electrodes generates polarization corresponding to a voltageapplied across the electrodes, and retains the polarization even afterthe applied voltage is removed. As the polarity of the applied voltageis reversed, the polarity of polarization is also reversed. By detectingthis polarization, information can be read. As the material of aferro-electric film, oxide ferro-electric material having the perovskitecrystal structure is used mainly, such as PZT(Pb(Zr_(1-x)Ti_(x))O₃) andSBT(SrBi₂Ta₂O₉) having a large polarization quantity, e.g., about 10μC/cm² to 30 μC/cm². In order to form an oxide ferro-electric filmhaving excellent characteristics, the film is required to be formed orto be subjected to heat treatment in an oxidizing atmosphere, and alower electrode (also an upper electrode when necessary) is often madeof noble metal hard to be oxidized, or noble metal maintainingconductivity even if it is oxidized or noble metal oxide.

Before a ferro-electric capacitor is formed, a MOS transistor is formedon a silicon substrate. When a ferro-electric capacitor is formed afterthe lower structure such as MOS transistors is formed, it is necessarythat the oxidizing atmosphere during formation of a ferro-electric filmshould not adversely affect the lower structure. For example, after MOStransistors are formed, the MOS transistors are protected by a film suchas a silicon oxynitride film having an oxygen shielding ability, and aninterlayer insulating film is formed on the oxygen shielding film.

The interlayer insulating film of a semiconductor integrated circuitdevice is made of silicon oxide in many cases. Silicon oxide has highaffinity with moisture. As moisture permeates from an external, moisturecan reach wirings, capacitors, transistors and the like through theinterlayer insulating film. As moisture reaches a capacitor particularlya ferro-electric capacitor, the characteristics of a dielectric filmparticularly a ferro-electric film are deteriorated. If theferro-electric film is reduced by hydrogen derived from permeatedmoisture and oxygen defects are formed, crystallinity becomes bad. Thecharacteristics are deteriorated such as a reduced residual polarizationquantity and a lowered dielectric constant. Similar phenomena occur bylong term use. As hydrogen permeates, deterioration of thecharacteristics becomes more direct than moisture. Silane used assilicon source for forming a silicon film or a silicon oxide film issilicon hydride, and generates a large amount of hydrogen whendecomposed. Hydrogen is also a factor of deteriorating a ferro-electricfilm.

In a standard ferro-electric capacitor having a structure that a PZTferro-electric film is sandwiched between lower and upper electrodesmade of Pt, it is known that ferro-electricity of the PZT film is almostlost if the substrate is heated to about 200° C. in an atmosphere at ahydrogen partial pressure of 40 Pa (0.3 Torr).

It is also known that the ferro-electricity of the ferro-electric filmis degraded considerably if heat treatment is performed on aferro-electric capacitor in a state that hydrogen or moisture isabsorbed in the capacitor or in a state that moisture exists near thecapacitor.

In manufacture processes for FeRAM, processes after the ferro-electricfilm is formed are so selected that generation of moisture and hydrogenis as less as possible and the process temperature is low. For example,a silicon oxide film is formed by chemical vapor deposition (CVD) usingtetraethoxysilane (TEOS) having a relatively small hydrogen generationamount, as Si source gas.

A process of forming a lower electrode just under the ferro-electricfilm is important in forming a ferro-electric capacitor. A conventionallower electrode has a structure that Ti and Pt are sequentiallylaminated on an insulating film. The Ti film improves adhesion betweenthe insulating film and the lower electrode. If the Ti film is not used,there is a high possibility that the Pt electrode is stripped or peeledoff. The Pt film is formed by sputtering. If this sputtering isperformed at a high temperature, the Pt film reacts with the Ti film,and will not cause (1 1 1) orientation, resulting in a randomly orientedstructure. If a TiO₂ film is used instead of the Ti film, reaction issuppressed so that the Pt film can be formed at a high temperature.However, as a TiO₂ film is formed on a degassed insulating film,crystallinity of the TiO₂ film is degraded, and crystallinity of the Ptfilm and ferro-electric film formed on the TiO₂ is lowered.

JP-A-2002-289793 (applicant: Fujitsu Limited), which is incorporatedherein by reference, proposes to use a lamination structure of a TiO₂film on an SiO₂ film, or an alumina film, as an insulating adhesionenhancing film under a Pt lower electrode.

JP-A-HEI-7-14993 (applicant: Mitsubishi Electric Corporation) proposes aDRAM semiconductor device using a high dielectric constant film such asSrTiO₃. It is pointed out that when a lower electrode of a flat planeshape is formed on an interlayer insulating film of silicon oxide formedwith an Si via conductor connected to a transistor and a high dielectricconstant film such as SrTiO₃ is formed on the interlayer insulatingfilm, covering the lower electrode, the high dielectric constant film islikely to be peeled or stripped off from the interlayer insulating film,and proposes to form an insulating adhesion enhancing film between theinterlayer insulating film and high dielectric constant film. Theinsulating adhesion enhancing film is made of TiO₂, ZrO₂, Ta₂O₅, Si₃N₄or Al₂O₃. After the insulating adhesion enhancing film is formed on thewhole surface of the interlayer insulating film, a polysilicon viaconductor is formed, a Pt lower electrode film is formed on theinsulating adhesion enhancing film, via a TiN barrier film whichprevents silicide reaction, and patterned. Thereafter a high dielectricconstant film is formed above the interlayer insulating film, coveringthe lower electrode, and an upper electrode layer common to a number ofcapacitors is formed on the high dielectric constant film.

JP-A-2005-39299 (applicant: Matsushita Electric Industrial Co. Ltd.)proposes, in a ferro-electric capacitor having a structure that aferro-electric film covers a lower electrode formed on an interlayerinsulating film and an upper electrode is formed on the ferro-electricfilm, to form a conductive hydrogen barrier film, covering the upperelectrode and having an overhang portion extending over the interlayerinsulating film. After an upper interlayer insulating film is formedcovering the ferro-electric capacitor, a via hole is formed reaching theoverhang portion of the conductive hydrogen barrier film, and aconductive plug is formed in the via hole. It teaches that it ispreferable to use, as the conductive hydrogen barrier film, a Ti film, aTa film, a TiON film, a TiN film, a TaN film, a TiAlN film, a TiAlONfilm or an alloy film containing these.

JP-A-2003-174146 (applicant: Fujitsu Limited), which is incorporatedherein by reference, proposes to form an upper electrode with alamination of two types of noble metal oxide films. Transistors formedon a semiconductor substrate are covered with an insulating barrier filmhaving an oxygen shielding ability such as a silicon nitride film and ansilicon oxynitride film in order to prevent an oxidizing atmosphereduring formation of the ferro-electric film from adversely affecting thetransistors. The ferro-electric capacitor is covered with an insulatingbarrier film having a hydrogen shielding ability such as alumina inorder to prevent the characteristics of the ferro-electric capacitorfrom being degraded by heat treatment in a reducing atmosphere.

SUMMARY

It is an aspect of the embodiments discussed herein to provide asemiconductor device including: a semiconductor substrate; asemiconductor element formed in the semiconductor substrate; aninsulating film covering the semiconductor element and formed above thesemiconductor substrate; a lower insulating hydrogen diffusionpreventive film having a hydrogen/moisture shielding function and formedabove the insulating film; a conductive adhesion enhancing film formedabove the lower insulating hydrogen diffusion preventive film; and aferro-electric capacitor including a lower electrode formed above theconductive adhesion enhancing film, a ferro-electric film formed on thelower electrode and being disposed within the lower electrode as viewedin plan, and an upper electrode formed on the ferro-electric film andbeing disposed within the ferro-electric film as viewed in plan, whereinthe conductive adhesion enhancing film has a function of improvingadhesion of the lower electrode of the ferro-electric capacitor andreducing leak current of the ferro-electric capacitor.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 1D are cross sectional views of a semiconductor substrateillustrating a method for manufacturing a semiconductor device accordingto a first embodiment.

FIGS. 2A to 2D are cross sectional views, an equivalent circuit diagram,and a graph explaining preliminary experiments made by the presentinventor and the measurement results.

FIGS. 3A to 3L are cross sectional views and graphs explainingexperiments made by the present inventor and the measurement results.

FIG. 4 is a cross sectional view showing a modification of the firstembodiment.

FIGS. 5A to 5E are graphs showing measurement results of samples of themodification.

FIGS. 6A to 6F are cross sectional views of a semiconductor substrateillustrating a method for manufacturing a semiconductor device accordingto a second embodiment.

DETAILED DESCRIPTION OF THE EMBODIMENTS

High integration and low voltage operation are required recently alsofor FeRAM. It is necessary for high integration to reduce an area of aferro-electric capacitor, and it is desired for low voltage operation tothin (reduce a thickness of) a ferro-electric film to raise an electricfield intensity upon unit voltage application. There may arise a problemof whether the expected characteristics can be maintained even if thearea of the ferro-electric film is reduced and a film thickness isthinned.

Prior to describing the embodiments of the present invention,experiments made by the present inventor will be described first. Withreference to FIGS. 2A to 2D, description will be made on preliminaryexperiments observing what influence appears when a capacitor cell sizeis reduced.

FIG. 2A shows a sample S1 of a capacitor formed by laminating a Pt filmon an insulating film, as a lower electrode LE via a Ti film interposedtherebetween as an adhesion enhancing layer CL, laminating on the Ptfilm, a PZT film as a ferro-electric film FD and a Pt film as an upperelectrode UE, and shaping into the capacitor of 50 μm×50 μm. Three typesof ferro-electric films were formed, one having a thickness of 200 nm asconventional thickness, and two having thicknesses of 150 nm and 120 nmwhich are thinned more than the conventional one.

FIG. 2B shows a sample S2 formed by depositing an interlayer insulatingfilm IL covering the sample S1 shown in FIG. 2A, forming contact holesand forming first metal wirings M1 connected to the upper electrode UEand lower electrode LE. As compared to the sample S1, processes areadded for interlayer insulating film formation, contact hole formationand first metal wiring formation.

FIG. 2C shows an equivalent circuit of a sample S3 of a capacitor cellarray CA connecting 1428 capacitors by first metal wirings, eachcapacitor Ci being a rectangle having a size of a longer side of 1.60 μmand a shorter side of 1.15 μm. The total area of the capacitor cellarray CA is 2500 μm² same as that of the samples S1 and S2. The sampleS3 corresponds to fine portions obtained by dividing the sample S2. Ascompared to the sample S2, processes are added for upper electrodeetching and ferro-electric film etching.

It can be considered that influence caused by additional processes canbe observed through comparison of the characteristics of the samples S1,S2 and S3. The samples S1, S2 and S3 were formed on the same wafer. Eachof two wafers was formed with each 20 samples of S1, S2, and S3 and aswitching charge quantity Q_(SW) was measured.

FIG. 2D is a graph showing measurement results. The abscissa shows threetypes of samples having different thicknesses of the ferro-electricfilm, and the ordinate represents a switching charge quantity S_(SW) inthe unit of C/cm². A measurement value of the sample S1 is indicated bya rhomb, a measurement value of the sample S2 is indicated by atriangle, and a measurement value of the sample S3 is indicated by arectangle.

At the conventional thickness of 200 nm of the ferro-electric film, thesamples S2 and S3 show similar values to those of the sample S1. It canbe understood that the process deterioration is negligible. At thethinned thickness of 150 nm and 120 nm of the ferro-electric film,measurement values of the samples S2 and S3 become smaller than those ofthe sample S1, indicating occurrence of the process deterioration. Asthe thickness of the ferro-electric film becomes thin, the switchingcharge quantity Q_(SW) itself reduces, and at the film thickness of 120nm, this quantity shows a value practically unusable. These resultssuggest that high integration and low voltage operation cannot berealized if conventional technologies are adopted.

If the Pt lower electrode of the ferro-electric capacitor is formeddirectly on the insulating film, peel-off of the electrode occurs. It issaid that an adhesion enhancing film should be formed between theinsulating film and Pt lower electrode. In addition to a conductive Tifilm as the adhesion enhancing film, there is a proposal to use aninsulating alumina (AlO) film or a titanium oxide (TiO) film. An aluminafilm is used also as a hydrogen diffusion preventive film by covering aferro-electric capacitor with the alumina film. It can be consideredthat the Ti film and alumina film have different functions. There is apossibility of new advantages if films having different functions arelaminated. In this context, samples were formed including a sampleformed with a Ti film under the Pt lower electrode, a sample formed withan alumina film under the Pt lower electrode, and a sample formed withan alumina film and a Ti film. First, a silicon oxide film having athickness of about 100 nm was formed by thermally oxidizing a siliconsubstrate surface. On the thermal oxide film, a silicon oxide film wasdeposited to a thickness of about 800 nm by chemical vapor deposition(CVD) using TEOS as source gas. Thereafter, annealing was performed for30 minutes at 650° C. in a nitrogen atmosphere to degas the siliconoxide film. These processes are common to respective samples. Thesilicon oxide film is denoted hereinafter as an insulating film INS.

FIG. 3A shows the structure of a sample S11 formed by depositing a Tifilm TI to a thickness of about 20 nm on an insulating film INS, andforming a Pt lower electrode LE, a PZT ferro-electric film FD and a Ptupper electrode UE on the Ti film.

FIG. 3B shows the structure of a sample S12 formed by depositing analumina film ALO to a thickness of about 20 nm on an insulating filmINS, and forming a Pt lower electrode LE, a PZT ferro-electric film FDand a Pt upper electrode UE on the alumina film.

FIG. 3C shows the structure of samples S13 and S14 formed by depositingfirst an alumina film ALO to a thickness of about 20 nm on an insulatingfilm INS, and forming a Ti film TI having a thickness of about 20 nm and10 nm respectively on the alumina film, and then forming a Pt lowerelectrode LE, a PZT ferro-electric film FD and a Pt upper electrode UEon the Ti film. Some measurements were conducted at the intermediatestage of forming the samples.

FIG. 3D is a graph showing values of the full width at half maximum(FWHM) of rocking curve of the Pt lower electrode LE of the (1 1 1)orientation measured by tetra-axis X-ray diffraction (XRD) after the Ptlower electrode LE is deposited to a thickness of 180 nm at a substratetemperature of 350° C. Measurements were conducted at five points,center, upper, lower, left and right of a wafer. The abscissa representsa measurement point, and the ordinate represents a full width at halfmaximum in the unit of degree. It indicates that the smaller the FWHMvalue, crystallinity is better. The sample S11 forming the Ti film of 20nm thick under the Pt film cab be considered as a standard sample. AFWHM value of the standard product is about 3.0 degrees. Crystallinityis degraded for the sample S12 changing the Ti film to the alumina filmunder the Pt film. The sample S13 inserting further the alumina filmunder the Ti film has a FWHM value about the same as that of thestandard sample, and influence of insertion of the alumina film uponcrystallinity is scarcely observed. Crystallinity improves slightly forthe sample which has a Ti film thinned to 10 nm.

PZT films having thicknesses of 150 nm and 120 nm were formed on the Ptlower electrodes LE by sputtering, and crystallized by rapid thermalannealing (RTA).

FIG. 3E is a graph showing FWHM values of the rocking curves of PZT filmof 150 nm thick on the (1 1 1) orientation measured by tetra-axis XRD.Similar to FIG. 3D, the abscissa represents five measurement points,center, upper, lower and left and right of a wafer, and the ordinaterepresents a FWHM value. A FWHM value of the standard product is about3.9 degrees. Influence upon (1 1 1) crystallinity is hardly observed forthe sample S12 changing the Ti film to the alumina film and the sampleS13 inserting the alumina film under the Ti film. (1 1 1) crystallinityof the PZT film is improved for the sample S14 thinning the Ti film to10 nm and inserting the aluminum film under the Ti film. In terms ofcrystallinity of the PZT film, the best results are given by the sampleinserting a two-layer structure of the Ti film laminated on the aluminafilm under the Pt lower electrode and thinning the Ti film.

FIGS. 3F and 3G are graphs showing measurement results of the switchingcharge quantity upon application of 3V to capacitors having a plan shapeof 50 μm×50 μm formed by forming a Pt upper electrode UE on PZT filmshaving thicknesses of 150 nm and 120 nm and patterning the upperelectrode and ferroelectric film. The abscissa indicates each sample,and the ordinate represents a switching charge quantity in the unit ofC/cm². A measurement value in the state that the ferro-electriccapacitor is formed is indicated by a rhomb, and a measurement value inthe state that the interlayer insulating film is formed and the firstmetal wirings are formed is indicated by a rectangle.

As compared to a sample 512 a forming a single layer alumina film undera Pt lower electrode and having a PZT film thickness of 150 nm, a sample511 a forming a single layer Ti film under a Pt lower electrode andhaving a PZT film thickness of 150 nm has a slightly higher switchingcharge quantity in the state of a capacitor, but reduces the switchingcharge quantity to almost the same as that of the sample S12 a after thefirst metal wirings are formed. This suggests occurrence of the processdeterioration. At the PZT film thickness of 120 nm, the processdeterioration of a sample S11 b having the Ti film increasesconsiderably as compared to a sample S12 b having the alumina film.

The samples S13 and S14 forming a lamination of the alumina film and aTi film under the Pt lower electrode have a large switching chargequantity and the process deterioration is scarcely recognized. Althoughthere is a possibility of influence of annealing used for wiringformation, an ability of providing a good switching charge quantity willnot change. Good results are obtained even if the PZT film is thinned.

FIGS. 3H and 3I show measurement values of a switching charge quantityof a cell array having PZT film thicknesses of 150 nm and 120 nm.Wirings are required for the cell array, and components up to the firstmetal wirings are formed. Two values of voltages of 3 V and 1.8 V wereapplied. The samples S13 and S14 forming the lamination film have largeswitching charge quantity as a whole, and have large switching quantityparticularly at an application voltage of 1.8 V. The sample S11 formingthe single layer Ti film has a switching charge quantity greatlydeteriorated for the thinned PZT film of 120 nm thick and an applicationvoltage of 1.8 V.

FIG. 3J is a graph showing a switching charge quantity of each sampleupon application of voltage. In a low voltage range, a rise is fast forTi film/alumina film lamination samples S13 b and S14 b with a thinnedPZT film of 120 nm. In a high voltage range, a saturated switchingcharge quantity is large for samples S13 a and S14 a having a laminationof a Ti film and an alumina film under a Pt lower electrode and a PZTfilm thickness of 150 nm. In order to obtain a large switching chargequantity, it is preferable to adopt the structure that a lamination of aTi film and an alumina film is formed under the Pt lower electrode.

FIGS. 3K and 3L show measurement values of leak current of each samplehaving a PZT film thickness of 150 nm and 120 nm. The abscissa indicateseach sample similar to that in FIGS. 3H and 3I, and the ordinaterepresents a leak current in the unit of A. The sample S12 using the AlOfilm as the adhesion enhancing film without the Ti film has quite alarge leak current. It can be considered that a leak current increasesgreatly if the Ti film is not formed under the Pt lower electrode. If aTiO film is used as the adhesion enhancing film, not only the leakcurrent is large, but also crystallinity of the lower electrode andferro-electric film formed on the adhesion enhancing film isdeteriorated, lowering a manufacture yield.

The leak current suggests existence of leak paths in the PZT film. Itcan be considered that a PZT film immediately after it is formed hasexcessive Pb and leak paths are formed. It can be estimated that if theTi film exists under the Pt lower electrode and Pb atoms diffuse, the Tifilm absorbs Pb atoms, and Ti atoms diffuse into the PZT film to filllattice defects. It can be considered that this phenomenon results in asmall leak current of the sample having the Ti film under the Pt lowerelectrode.

If only the Ti film is formed under the Pt lower electrode, the processdeterioration is large as indicated by the sample S11 shown in FIGS. 3Fand 3G and FIGS. 3H and 3I. It can be estimated that hydrogen andmoisture permeate from under the lower electrode and crystallinity ofthe ferro-electric film is deteriorated. It can be considered that ifthe alumina film is further disposed under the Ti film, moisturediffusion can be prevented and crystallinity of the ferro-electric filmcan be suppressed from being deteriorated.

The material of a conductive adhesion enhancing film capable ofsupplying Ti and absorbing excessive compositions of the ferro-electricfilm may be, in addition to Ti, Ti-containing TiN, TiAlN and TiAlON. Theconductive adhesion enhancing film can be formed by physical depositionsuch as sputtering and electron beam deposition or by physical chemicaldeposition such as reactive sputtering.

The material of the insulating hydrogen diffusion preventive filmcapable of preventing diffusion of hydrogen and moisture is not limitedonly to alumina (aluminum oxide (AlO), but it is expected to beeffective to use also aluminum nitride (AlN), titanium-aluminum nitride(TiAlN), tantalum oxide (TaO), titanium oxide (TiO) and zirconium oxide(ZrO). The insulating hydrogen diffusion preventive film can be formedby physical deposition such as sputtering, by chemical deposition suchas CVD and by physical chemical deposition such as reactive sputtering.

FIGS. 1A to 1D illustrate a method for manufacturing the semiconductordevice of the first embodiment of the present invention based on theabove-described experiment results and show a manufactured semiconductordevice.

As shown in FIG. 1A, in the surface layer of a semiconductor substrate 1such as a silicon substrate, an isolation region defining active regionsis formed, for example, by local oxidation of silicon (LOCOS). A p-typewell is formed in the region where an n-channel transistor is to beformed, and an n-type well is formed in the region where a p-typetransistor is to be formed. Description will be made hereinafter onforming an n-channel transistor by way of example. For the p-channeltransistor, conductivity types are reversed.

The surfaces of active regions are thermally oxidized to form a gateoxide film 3 having a thickness of, e.g., 10 nm. A polysilicon film 4and a silicide layer 5 of WSi₂ are formed on the gate oxide film 3 andpatterned to a gate electrode structure. By using as a mask thepatterned gate electrode and a resist pattern formed when necessary,n-type ions are implanted at a low acceleration energy to formextensions EX of source/drain S/D. A silicon oxide film is deposited onthe substrate, and anisotropically etched by reactive ion etching or thelike to form side wall spacers 6 on side walls of the gate electrode.

By using the gate electrode formed with the side wall spacers and aresist pattern formed when necessary, as a mask, n-type ions areimplanted at a high dose to form high concentration regions HD of thesource/drain S/D. The silicide layer 5 on the polysilicon layer 4 maynot be formed beforehand, and a metal film capable of silicide such asCo may be deposited at this stage and annealed to form a silicide layer.

An insulating oxygen barrier layer 7 of silicon oxynitride or the likehaving an oxygen diffusion preventive function is formed covering theMOS transistors formed in the manner described above. A silicon oxidefilm 8 is further deposited to a thickness of, e.g., about 700 nm by CVDusing TEOS. If necessary, the surface of the silicon oxide film isplanarized by chemical mechanical polishing (CMP) or the like. Annealingis performed for 30 minutes at 650° C. in a nitrogen atmosphere to degasthe silicon oxide film 8. The above-described processes are well knownprocesses of CMOS semiconductor device manufacture, and well knownchange, addition, modification and the like may be made.

On the silicon oxide film 8, an insulating hydrogen diffusion preventivefilm 11 of alumina or the like is deposited to a thickness of about 20nm, for example, by sputtering. When considering workability, athickness of the alumina film is preferably not thicker than 100 nm, andgenerally be in a range of 20 nm to 50 nm. When a dense film is formedby CVD or the like, the film thickness may further be thinned. Also inthis case, it is desired that a thickness of the insulating hydrogendiffusion preventive film is not thinner than 1 nm.

On the insulating hydrogen diffusion preventive film 11, a conductiveadhesion enhancing film 12 of Ti or the like is deposited to a thicknessof about 10 nm by sputtering at a substrate temperature of 150° C. Apreferable temperature at which the Ti film is formed is in a range from10° C. to 200° C. A thickness of the Ti film is preferably 1 to 25 nm.As the Ti film is made thick to 30 nm or more, crystalline orientationof a lower electrode and ferro-electric film to be formed on the Ti filmwill be degraded.

On the conductive adhesion enhancing film, a lower electrode of Pt orthe like is deposited to a thickness of about 180 nm by sputtering. Asubstrate temperature is preferably in a range of 100° C. to 350° C. Onthe lower electrode, a ferro-electric film FD of PLZT ((Pb, La)(Zr,Ti)O₃ or the like is deposited in an amorphous state to a thickness ofabout 100 to 200 nm by RF sputtering. RTA is performed at a temperaturenot higher than 650° C. in an atmosphere containing Ar and O₂, and RTAis further performed at 750° C. in an oxygen atmosphere. With theseannealing processes, the ferro-electric film FD is crystallized and thelower electrode LE is densified. Mutual diffusion of Pt and 0 istherefore suppressed at the interface between the lower electrode LE andferro-electric film FD. Furthermore, excessive Pb in the ferro-electricfilm FD is diffused into the conductive adhesion enhancing film and Tiin the conductive adhesion enhancing film diffuses or intrudes up intothe ferro-electric film, to stabilize the composition of theferro-electric film.

An upper electrode UE is formed on the ferro-electric film FD. Forexample, while Ar and O₂ are flowed at a flow rate of about 100 sccm ata substrate temperature of about 300° C., a crystallized IrO film havinga thickness of about 50 nm is formed by reactive sputtering. On the thisIrO film, an IrO film is further formed to a thickness of about 200 nmby sputtering. The latter IrO film is not required to be crystallizedwhen the film is formed.

The rear surface of the substrate is cleaned, and the upper electrode UEis patterned. Annealing is performed for 60 minutes at 650° C. in an O₂atmosphere to recover damages occurred in the ferro-electric film.Thereafter, the ferro-electric film FD is patterned. A hydrogendiffusion preventive film 16 of alumina or the like is deposited bysputtering, covering the patterned, separated and divided ferro-electricfilm FD and upper electrode UE. Annealing is performed in an oxygenatmosphere and thereafter, the hydrogen diffusion preventive film 16 ofalumina or the like and lower electrode LE are patterned at the sametime. Annealing is performed in an oxygen atmosphere to tightly adherethe hydrogen diffusion preventive film.

The ferro-electric film FD is patterned in a shape retracting from theperipheral edge of the patterned lower electrode LE, whereas the upperelectrode is patterned in a shape retracting from the peripheral edge ofthe ferro-electric film FD. The ferro-electric film FD is patterned toremain only on the lower electrode LE in a plan view, i.e. beingencompassed in the lower electrode area and not protruding outside thelower electrode LE.

A hydrogen diffusion preventive film 17 of alumina or the like isfurther deposited on the whole substrate surface by sputtering, coveringthe ferro-electric capacitor formed in the manner described above, andannealing is performed in an oxygen atmosphere. Several annealingprocesses stabilize the composition of the ferro-electric film andsuppress leak current.

An interlayer insulating film 18 of silicon oxide is deposited to athickness of about 1.5 μm by high density plasma CVD, covering theferro-electric capacitor, and the surface of the interlayer insulatingfilm is planarized by CMP. Plasma annealing is performed by using N₂Ogas to slightly nitrify the interlayer insulating film. A moistureshielding function is therefore provided. The plasma process may beperformed in gas containing either N or O, in place of N₂O.

A resist pattern is formed on the interlayer insulating film 18, andcontact holes CH are formed by etching through the interlayer insulatingfilm 18, hydrogen diffusion preventive films 17 and 11, silicon oxidefilm 8, and silicon oxynitride film 7, reaching the source/drain regionS/D. A Ti film and a TiN film are deposited by sputtering to form abarrier metal film BM, and thereafter a main conductive film MM of ablanket W film is deposited by CVD.

As shown in FIG. 1B, unnecessary conductive film on the interlayerinsulating film 18 is removed to form W plugs PL flush with the surfaceof the interlayer insulating film 18. A silicon oxynitride film 21 isdeposited on the interlayer insulating film 18 by plasma enhanced (PE)CVD, covering the plug PL, to thereby form an oxidation preventive filmfor the W plug PL.

As shown in FIG. 1C, a resist pattern is formed on the siliconoxynitride film 21, and contact holes CH are formed by etching throughthe silicon oxynitride film 21, interlayer insulating film 18 andhydrogen diffusion preventive films 17 and 16, reaching the upperelectrode UE and lower electrode LE. Annealing is performed in an oxygenatmosphere to recover damages.

As shown in FIG. 1D, the resist pattern is removed, and the siliconoxynitride film 21 is removed by etch-back to expose the surfaces of theW plug PL. A wiring layer of aluminum or aluminum alloy is formedburying the contact holes, and etched by using a resist pattern as amask to form metal wirings M1. In the structure shown, a memory cell isformed by connecting one of the source/drain regions S/D and the lowerelectrode LE of the ferro-electric capacitor. Further interlayerinsulating films and wirings may be formed according to necessity.

According to this embodiment, the conductive adhesion enhancing film ofTi or the like is disposed under the lower electrode LE, and theinsulating hydrogen diffusion preventive film of alumina or the like isdisposed under the conductive adhesion enhancing film. Since not onlythe upper surface and side walls of the ferro-electric capacitor arecovered with the upper insulating hydrogen diffusion preventive film butalso the bottom surface of the capacitor is also covered with the lowerinsulating hydrogen diffusion preventive film, there is no path alongwhich hydrogen and/or moisture can permeate, and the processdeterioration and environmental influence are hard to occur. Since theconductive adhesion enhancing film is disposed on the lower insulatinghydrogen diffusion preventive film, leak current can be suppressed. Evenfor a micro structure, an excessive reduction in switching charges canbe suppressed, and the invertible charge quantity can be improved. It ispossible to lower a coercive voltage or coercive field and improvedurability against fatigue and imprint.

FIG. 4 shows an integrated CMOS circuit according to a modification ofthe first embodiment. A CMOS logic circuit together with a transfertransistor of a memory cell are formed. The right side of FIG. 4 shows aferroelectric memory structure similar to that shown in FIG. 1D. Theleft side of FIG. 4 shows the CMOS logic circuit. In active regionsdefined by an isolation region, a p-type well PW and an n-type well NWare formed. In the p-type well PW, an n-channel transistor NMOS isformed. In the n-type well NW, a p-channel transistor PMOS of anopposite conductivity type is formed. The transistors are covered withthe silicon oxynitride film 7 and silicon oxide film 8, and the lowerinsulating hydrogen diffusion preventive film 11 and conductive adhesionenhancing film 12 are formed on the silicon oxide film.

A Pt lower electrode LE is formed on the conductive adhesion enhancingfilm 12, and a PZT ferro-electric film FD having a thickness of 120 nmis formed on the lower electrode LE. A Pt upper electrode UE is formedon the ferro-electric film FD, and the insulating hydrogen diffusionpreventive film 17 and interlayer insulating film 18 are deposited onthe whole substrate surface.

Contact holes for source/drain of a transfer transistor and contactholes for CMOS transistors are formed at the same time, and W plugs areburied in the contact holes. An inverter is connected by a first metalwiring.

Samples of an integrated CMOS circuit were formed. The insulatinghydrogen diffusion preventive film 11 was formed by an alumina filmhaving a thickness of 20 nm, the conductive adhesion enhancing film 12was made of Ti, and two types of the conductive adhesion enhancing filmswere formed having thicknesses of 20 nm and 10 nm. A sample having a Tilayer of 20 nm thick is called a sample S23, and a sample having a Tilayer of 10 nm is called a sample S24. Measurement values are shown inFIGS. 5A to 5E.

FIG. 5A shows a switching charge quantity of samples having a capacitorarea of 50 μm×50 μm upon application of 3 V. FIGS. 5B and 5C showmeasurement values of a switching charge quantity of capacitor cellarrays upon application of 3 V and 1.8 V. FIG. 5D shows measurementvalues of leak current of the cell arrays. In FIGS. 5A to 5D, ameasurement value of the sample formed up to the first layer metalwirings is indicated by a rhomb, and a measurement value of the sampleformed up to the third layer metal wirings is indicated by a triangle.FIG. 5E shows a change in a switching charge quantity with an appliedvoltage.

As shown in FIG. 5A, the capacitor having an area of 50 μm×50 μm isscarcely deteriorated by multilayer wirings. As shown in FIGS. 5B and5C, although the switching charge quantity lowers slightly from firstlayer metal wiring formation to third layer metal wiring formation, itcan be said that the switching charge quantity is almost at the samelevel. As shown in FIG. 5E, at a Ti conductive adhesion enhancing filmthickness of 10 nm, a rise of Qsw is fast, and a switching chargequantity at a low voltage becomes large. As shown in FIG. 5D, a leakcurrent of the cell capacitor reduces with wiring formationindependently from a Ti film thickness. It may be said that a leakcurrent hardly increases when considering the annealing effects. Theadvantages were observed in a low resistance voltage, an improved Qsw, alow leak current and suppression of the process deterioration.

A yield of 80% was obtained for the sample having a Ti film thickness of20 nm. A yield of 83% was obtained for the sample having a Ti filmthickness of 10 nm. It can be considered that improvement ofcrystallinity can be expected from a reduction in a Ti film thickness,being reflected upon a yield.

Description has been made on forming a planar type ferro-electriccapacitor on an insulating film. A stack type is also possible, whereina ferro-electric capacitor is formed on a conductive plug. In thefollowing, with reference to FIGS. 6A to 6F, description will be made onthe second embodiment in which a stack type ferro-electric capacitor isformed.

As shown in FIG. 6A, an isolation region 2 is formed in the surfacelayer of a semiconductor substrate 1 such as a silicon substrate byshallow trench isolation (STI) or the like. Ions are implanted to from ap-type well PW and an n-type well NW.

MOS transistor structures are formed by processes similar to those ofthe first embodiment. Namely, a gate oxide film 3 is formed by thermallyoxidizing the active region surfaces, and a polysilicon film 4 and asilicide film 5 are formed and patterned to form gate electrodes. Ann-type gate electrode is formed above the p-type well, and a p-type gateelectrode is formed above the n-type well. Impurity ions of n-type areimplanted into the p-type well to form extensions of n-typesource/drain. Impurity ions of p-type are implanted into the n-typewell. An insulating film such as silicon oxide is deposited, andanisotropic etching is performed to form side wall spacers 6. Highconcentration source/drain regions are formed by implanting n-typeimpurity ions into the p-type well and p-type impurity ions into then-type well, respectively at a high concentration.

These processes are well known CMOS manufacture processes, and otherwell known processes may also be used. Two NMOSs shown have a centralsource/drain region as a common region for both NMOSs.

A silicon oxynitride film 7 having a thickness of 200 nm is deposited byCVD, covering the MOS transistors. A silicon oxide film 8 having athickness of 1000 nm is deposited on the silicon oxynitride film by CVD,and planarized by CMP. Annealing is performed for 30 minutes at 650° C.in a nitrogen atmosphere to degas. An insulating hydrogen diffusionpreventive film 11 of aluminum oxide having a thickness of about 50 nmis formed on the silicon oxide film 8 by sputtering. Instead of aluminumoxide, the insulating hydrogen diffusion preventive film 11 may be madeof aluminum nitride, TiAlN, tantalum oxide, titanium oxide or zirconiumoxide.

As shown in FIG. 6B, a resist pattern is formed on the insulatinghydrogen diffusion preventive film 11, and contact holes CH are formedby etching reaching the source/drain regions of the MOS transistors. Thecentral source/drain region will be connected to a bit line, and outersource/drain regions will be connected to capacitors. Annealing isperformed for 30 minutes at 650° C. in a nitrogen atmosphere. A Ti layerof 20 nm thick, a TiN layer of 50 nm thick and a Ti layer of 20 nm thickare formed by sputtering to form a barrier layer BM serving also as anadhesion enhancing layer. On the barrier film BM, a W film is formed toa thickness of 300 nm by CVD to bury the contact holes CH.

As shown in FIG. 6C, the conductive layer on the insulting hydrogendiffusion preventive film 11 is removed by low pressure polishing (CMP)or electrolytic mechanical polishing (ECMP), and conductive plugs PL1are left in the contact holes. By using the low pressure polishing CMPor electrolytic mechanical polishing ECMP and the aluminum oxide film asa stopper, the W plug surface having good flatness is obtained which isat the same level as that of the surrounding insulating film surface.

As shown in FIG. 6D, a conductive adhesion enhancing film 12 of a Tifilm not thicker than 25 nm, a conductive oxygen barrier film 14 and alower electrode LE are formed on the aluminum oxide film 11, coveringthe W plugs PL1. Since the underlying layer is flat, a film of goodcrystallinity can be formed. For example, the conductive oxygen barrierfilm 14 is a film made of noble metal Ir, Ru or TiAlN having a thicknessof 100 to 200 nm. By forming the oxygen barrier film, it becomespossible to prevent oxygen from diffusing into the W plugs duringformation of the ferro-electric film or during crystallizationannealing. Instead of the Ti film, a TiN film, a TiAlN film or a TiAlONfilm may also be used as the conductive adhesion enhancing film. Thelower electrode LE is made of a Pt film having a thickness of about 50to 200 nm. The lower electrodes may be made of material selected from agroup consisting of Pt, Ir, Ru, Rh, Re, Os, Pd, oxide thereof, andSrRuO₃.

A ferro-electric film FD of a PZT film of 120 nm thick is formed on thelower electrode LE by MOCVD. For example, MOCVD is performed at a filmforming temperature of 650° C. and an oxygen partial pressure of 5 Torr,by using as a Pb source, Pb(DPM)2((DPM: di-pivaloylmethanate) at 0.32ml/min, as a Zr source, tetrakis (dmhd: di-methylhexanedionate) at 0.3ml/min, and as a Ti source,titanium-di-(iso-propoxy)-bis-(di-pivaloylmethanate)Ti(O-iPr)2(DPM)2(iPr: iso-propoxy) at 0.2 ml/min. The sources are dissolved inTHF (tetrahydrofuran) at a mol ratio of 3%, and transported in a liquidstate to a vaporizer. THF and sources were vaporized at a vaporizingtemperature of 260° C., mixed with oxygen, and blown to a wafer via ashower head. A film formation time was set to 420 seconds. Thecomposition of the PZT film obtained by MOCVD was Pb/(Zr+Ti)=1.15,Zr/(Zr+Ti)=0.45.

Ferro-electric film material may be PZT, SBT and Bi-containing layeredcompound which contain a small amount of additive such as La, Ca, Sr andSi, and include PZT, BLT and PLZT expressed by a general formula ofABO₃.

After the ferro-electric film is formed, annealing is performed in anoxygen-containing atmosphere for crystallization. For example, an RTAprocess is performed including first annealing for 90 seconds at asubstrate temperature of 600° C. in an atmosphere of mixture gas of Arand O₂ and second annealing for 90 seconds at a substrate temperature of750° C. in an oxygen atmosphere. These annealing processes do notinfluence the contact plugs. Noble metal becomes conductive oxide evenif it is oxidized. Since the conductive oxygen barrier film exists underthe lower electrode, oxygen diffusion can be prevented, An upperelectrode UE is formed on the ferro-electric film FD by forming aniridium oxide film having a thickness of, e.g., 200 nm by sputtering.The upper electrode may be a single layer or a plurality of layers of atleast one metal or metal oxide selected from a group consisting of Pt,Ir, Ru, Rh, Re, Os, Pd and SrRuO₃.

As shown in FIG. 6E, the upper electrode UE, ferro-electric film FD,lower electrode LE, conductive oxygen barrier film 14 and conductiveadhesion enhancing film 12 are sequentially patterned by hightemperature or room temperature etching by commonly using a hard mask.After etching, the hard mask is removed. Annealing is performed for onehour at 350° C. in an oxygen-containing atmosphere. An insulatinghydrogen diffusion preventive film 17 of aluminum oxide or the like isformed to a thickness of 20 to 100 nm by sputtering or CVD, covering theferro-electric capacitor. Damage recovering annealing is performed at550° C. to 650° C. in an oxygen-containing atmosphere. Thereafter, aninterlayer insulating film 18 is formed and its surface is planarized byCMP.

As shown in FIG. 6F, contact holes are formed by etching, reaching thecentral W plug PL1 and the upper electrode of the ferro-electriccapacitor, and W plugs PL2 buying the contact holes are formed byprocesses similar to those for PL1. Similar processes are repeated toform multilayer wirings of a desired number of layers.

According to the embodiment, the ferro-electric capacitor is formed onthe insulating film burying therein the conductive plugs. Since theunderlying surface is highly planarized, it is possible to form thelower electrode and ferro-electric film without degrading crystallinity.Since the conductive adhesion enhancing film and insulating hydrogendiffusion preventive film are formed under the lower electrode, theadvantages similar to the first embodiment can be expected. Since theconductive oxygen barrier layer is disposed under the lower electrode,it is possible to prevent oxygen from reaching the conductive plugsduring the ferro-electric film forming process.

Since a lamination of the conductive adhesion enhancing film andinsulating hydrogen diffusion preventive film is disposed under thelower electrode of the ferro-electric capacitor, durability againsthydrogen and moisture can be increased so that a semiconductor devicehaving a ferro-electric capacitor can be obtained which has small leakcurrent and less process deterioration.

The present invention has been described in connection with thepreferred embodiments. The invention is not limited only to the aboveembodiments. It will be apparent to those skilled in the art that othervarious modifications, improvements, combinations, and the like can bemade.

1.-11. (canceled)
 12. A method for manufacturing a semiconductor devicecomprising steps of: (a) depositing an insulating oxygen barrier layerand an interlayer insulating film on a semiconductor substrate formedwith a transistor; (b) forming an insulating hydrogen diffusionpreventive film above said interlayer insulating film; (c) forming aconductive adhesion enhancing film containing Ti above said insulatinghydrogen diffusion preventive film; (d) forming a ferro-electriccapacitor including a lamination of a lower electrode, a ferro-electricfilm and an upper electrode, with an upper layer not protruding outsidea lower layer, above said conductive adhesion enhancing film; and (e)performing annealing in an oxygen-containing atmosphere after said step(d).
 13. The method for manufacturing a semiconductor device accordingto claim 12, wherein said step (b) forms, by physical deposition orchemical deposition, a film made of at least one material selected froma group consisting of aluminum oxide, aluminum nitride, TiAlN, tantalumoxide, titanium oxide and zirconium oxide.
 14. The method formanufacturing a semiconductor device according to claim 13, wherein saidstep (b) forms an aluminum oxide film having a thickness of 1 to 100 nm.15. The method for manufacturing a semiconductor device according toclaim 12, wherein said step (c) forms, by physical deposition orchemical deposition, a film made of at least one material selected froma group consisting of Ti, TiN, TiAlN and TiAlON.
 16. The method formanufacturing a semiconductor device according to claim 15, wherein saidstep (c) form a Ti film by sputtering.
 17. The method for manufacturinga semiconductor device according to claim 16, wherein said step (c)performs sputtering at a substrate temperature of 10 to 200° C.
 18. Themethod for manufacturing a semiconductor device according to claim 12,further comprising steps of: (f) forming conductive plugs through saidinsulating hydrogen diffusion preventive film, said interlayerinsulating film and said insulating oxygen barrier film and reachingsaid transistors, between said steps (b) and (c); and (g) forming aconductive oxygen barrier layer on said conductive adhesion enhancingfilm, between said steps (c) and (d).
 19. The method for manufacturing asemiconductor device according to claim 18, wherein said step (f)comprises steps of: (f-1) forming contact holes by etching through saidinsulating hydrogen diffusion preventive film, said interlayerinsulating film and said insulating oxygen barrier layer; (f-2)depositing plug material burying said contact holes; and (f-3) removingsaid plug material on said insulating hydrogen diffusion preventive filmby polishing, by using said insulating hydrogen diffusion preventivefilm as a stopper.
 20. The method for manufacturing a semiconductordevice according to claim 19, wherein said step (f-3) is low pressurechemical mechanical polishing or electrolytic mechanical polishing.